IBM says it’s built the world’s first sub-1 nanometer chip technology, packing nearly 100 billion transistors onto a chip the size of a fingernail. That’s nearly twice the density of their previous generation. But the number needs some unpacking.
Let’s be clear: nobody is building transistors smaller than 1 nanometer in any physical sense. The “sub-1 nanometer” label refers to IBM’s “nanostack” architecture, which vertically stacks transistors in a staggered layout to deliver the performance gains you’d theoretically expect from a 0.7-nanometer process — what IBM calls the 7 angstrom node.
“It’s not just an incremental step, it’s a meaningful leap forward,” said Jay Gambetta, director of IBM Research. He described it as pointing to “a future where computing becomes significantly more powerful without a corresponding increase in energy.”
Each basic unit stacks two transistors bonded together. Each transistor uses three nanosheets, individually 5 nanometers thick — about 15 rows of silicon atoms — separated by roughly 9 nanometers. The architecture builds on IBM’s prior nanosheet transistor work that led to their 2-nanometer node in 2021.
The projected gains are significant: 50% higher computing performance or 70% greater energy efficiency compared to IBM’s 2-nanometer chips. IBM researchers also demonstrated a 40% improvement in SRAM scaling, which matters for AI workloads that rely heavily on fast memory access.
Node numbers haven’t corresponded to actual physical dimensions for decades — a “3-nanometer” chip doesn’t have 3-nanometer features. IBM’s naming follows the industry convention of using node names as performance benchmarks rather than literal measurements. The real story is the vertical stacking approach, which sidesteps the physical limits that have been slowing down traditional transistor shrinking.
