IBM just built a prototype chip packing around 100 billion transistors onto a fingernail-sized piece of silicon. That’s twice the density of their previous best, announced in 2021. The trick? They stopped shrinking transistors and started stacking them.
For decades, Moore’s Law meant one thing: make transistors smaller. But we’re hitting a wall. At just a few dozen nanometers, quantum mechanics starts interfering with how transistors work. They can’t get much smaller.
So the industry is pivoting to an approach city planners figured out long ago: build up. IBM’s new “nanostack” architecture vertically stacks two layers of transistors on a single silicon chip. The company says chips built this way can do 50% more work in the same time while using up to 70% less energy.
“It’s not just an incremental step,” said Jay Gambetta, director of IBM Research. “It’s a meaningful leap forward.”
Intel, Samsung, and TSMC are all pursuing similar CFET (complementary field-effect transistor) designs. IBM’s approach staggers the second layer of transistors rather than placing them directly on top of the first, which simplifies wiring.
The challenges are real. Stacking layers means higher failure rates during manufacturing. And there’s the thermal problem – building each layer without melting the connections underneath requires keeping processes below 400 degrees Celsius. IBM figured out how, though they’re not sharing the details.
If Gambetta is right, nanostacked chips could be common in data centers within ten years. That’s good news for an industry desperate to improve energy efficiency.
